1. Field of Invention
The present invention relates to a circuit for maintaining the input common-mode voltage of a differential input amplifier, and more particularly, to an input common-mode feedback circuit applicable to a differential input amplifier and a fully differential sensing apparatus applying the aforementioned input common-mode feedback circuit.
2. Description of the Related Art
In the field of capacitive sensing applications, the sensed parameters can be dielectric constant, capacitance gap distance or capacitance area. Very often at least one of these parameters changes corresponding to an external stimulus. The sensed stimulus (for example, physical quantities such as pressure, movement or dielectric constant between sensing capacitor electrodes) can be very small to detect. Therefore it is helpful to lower the noise floor in the detection interface circuitry to allow enough signal range to detect. The often used technique of synchronous modulation and demodulation is to bring the baseband signal to a higher carrier frequency where flicker noise (or 1/f noise) is essentially lower to enhance signal to noise ratio (SNR), amplify the modulated signal at lower noise floor and restore modulated signal to baseband signal by demodulation and low pass filtering.
The sensing capacitors are intrinsically small voltage sources with very high output capacitive impedance compared to more typical voltage sources with low output resistive impedance. Two types of amplifiers are often used to convert such a high output impedance voltage source to a low output impedance voltage source for further amplification and voltage signal processing. One of these two types of amplifier configurations is a high impedance amplifier that presents, in a closed-loop buffer configuration, very high input impedance in order to take signal voltage from the capacitive source(s) within negligible portion of time constant of capacitive source and its high impedance path to an ac ground point on its charging loop. That is, net charge flow will be mostly constrained to nearly zero. When the nominal value of the capacitive source changes with external stimulus, the constrained charge will hence allow a corresponding ac voltage on the capacitive source. The other type of amplifier is a low impedance amplifier that presents, in a closed-loop integrator configuration, very low input impedance in order to take most charge flow from capacitive source(s), integrate it through a feedback capacitor and make it a voltage output at low impedance amplifier's output stage. Our proposed invention introduced new interface circuit architecture for the latter type of capacitive amplifier, particularly implemented with differential input configuration.
The capacitive source when biased at a fixed cross-terminal voltage can only hold fixed charges. The cross-terminal voltage is usually established by a biasing voltage at one of its capacitor plate and a reference voltage at the other plate connected to an input node of a low impedance amplifier. Whenever the nominal capacitance of sensing capacitor changes due to an external stimulus, the charges must be provided or go away and hence a charge flow goes into/from the capacitive source(s) from/to the input node(s) of the aforementioned low impedance amplifier. The higher the cross-terminal biasing voltage is, the larger the charge flow will be integrated through a feedback capacitor and hence larger baseband voltage can be generated at the low impedance amplifier's output stage when given the same nominal source capacitance change.
FIG. 1 is a circuit diagram of a conventional fully differential charge integration amplifier. Referring to FIG. 1, the fully differential charge integration amplifier 100 comprises a differential capacitive pair cs1 and cs2, feedback integration capacitors cf1 and cf2 and a fully differential input amplifier 101. FIG. 2 is a diagram of a conventional charge integration amplifier and its input common-mode feedback circuit based on the principle of charge cancellation at the input nodes of the main amplifier 101.
The synchronous modulation technique mentioned above for capacitive sensing is often implemented for the low impedance amplifier by modulating the biasing voltage at a higher carrier frequency. It has been described above that fixed amount of charge resides on the nominal capacitive source biased by a fixed cross-terminal voltage. When an unbalanced condition happens due to external stimulus to cause nominal capacitance change, it is desired that most charge flow goes through the feedback integration capacitor (Cf1 and Cf2 in FIG. 1) in order to obtain more useful voltage signal range. This can be achieved by minimizing the parasitic capacitance between capacitive source and the input node of the low impedance amplifier and also by virtual-shorting the input nodal voltage to a set input common mode voltage of the low impedance amplifier to make the amplifier's input node a nearly zero impedance ac ground node to maintain accurate biasing voltage across the source capacitor and to shield the parasitic capacitive leakage path at amplifier's input node(s). When the biasing voltage is modulated at a carrier frequency much higher than the baseband frequency, charge flow starts to flow in and out much faster than when biasing voltage is a fixed value. If no enough charges can be provided and/or removed in a timely manner, the cross-terminal voltage of the nominal capacitance will very possibly not be able to be maintained or in another word, the input common mode voltage of low impedance amplifier can quickly move away until the amplifier fails to work normally.
Often used solution to mitigate this addressed problem is to setup two differential capacitive sources in a pair configuration by applying two out-of-phase modulated biasing voltages at outer terminals of the capacitive source pair and taking the middle node of the pair to the inverting node of a single-ended low impedance amplifier, or in the differential input configuration, to set up four differential capacitive sources in a Wheatstone bridge fashion (i.e. to shunt one differential capacitive source pair with the other in a reversed direction) by applying two out-of-phase modulated biasing voltages at the outer terminals of two differential capacitive source pairs and taking two middle nodes of the Wheatstone bridge to the input nodes of a differential low impedance amplifier. The opposite charge flows due to the out-of-phase modulated biasing voltages will be quickly nulled out in the middle node(s), hence induce little operating point shift at these middle node(s) that is/are connected to the low impedance amplifier input node(s).
The third solution proposed by Lemkin and Boser et al is to setup a differential capacitive pair (Cs1 and Cs2 in FIG. 1), apply a single modulated biasing voltage (Vstep in FIG. 1) at middle of this capacitive source pair and connect the outer terminals of capacitive source pair to the input nodes of a differential low impedance amplifier (101 in FIG. 1). But an error amplifier (201a in FIG. 2) with two local feedback capacitors (Cb1 and Cb2 in FIG. 2) which are connected between error amplifier's output and differential low impedance amplifier's input nodes is required to amplify the error voltage between a set common mode voltage (Vicm in FIG. 2) and measured common mode voltage at low impedance amplifier's input nodes. The error amplifier and two local feedback capacitors forms a negative feedback loop and compose an input common mode feedback (ICMFB) circuit for the low impedance amplifier. Opposite charge will be injected to the outer terminals (or input nodes of the differential input amplifier) of the differential capacitive source pair by the amplified error voltage (alpha*Vstep in FIG. 2) through the error amplifier's local feedback capacitors (Cb1 and Cb2 in FIG. 2) in order to restore the input common mode voltage of the differential low impedance amplifier back to the set value for normal operation. And a defined high impedance path will be needed in shunt with the low impedance amplifier's integration capacitors (Cf1 and Cf2 in FIG. 1) to properly maintain a stable dc operating point at its input nodes. The output voltage, deltaV(ΔV), can be estimated by the formula listed below where Cf is the feedback integration capacitor, deltaC(ΔC) is source capacitance change and Vbias=Vstep−Vicm is the cross-terminal biasing voltage if the input common mode voltage is set at a zero reference voltage (Vicm=0V).Δ∝Vstep×(ΔC/Cf)
The first two aforementioned solutions will have degraded performance if mismatch between source capacitors exists. The third proposed solution explained in the previous paragraph requires engineering tuned combination of Cs and Cb and alpha parameters so that opposite charges through Cs and Cb can exactly cancel with each other at the input nodes of low impedance amplifier and thus no input common mode voltage change will be caused. In case that the nominal capacitive sources (Cs1 and Cs2) can be application dependent, or field dependent, the best parameter combination cannot be maintained for all applications thereof, hence the input common mode voltage of the differential low impedance amplifier can move up and down with the modulated biasing voltage, Vstep. Thus not only will signal strength be reduced but also unwanted distortions can be generated herewith. Although resistors in shunt with Cf1 and Cf2 can help to lessen this input common mode movement with modulated biasing voltage, yet a high pass corner of Whpc decided by the Cf and shunt resistor Rf (Whpc=1/(Cf*Rf)) can be a limitation to lower the time constant of Cf*Rf where this time constant should be otherwise small enough compared to the modulating biasing voltage period. That is, to achieve smaller Cf*Rf time constant will inevitably hurt the transfer gain below Whpc. Generally speaking, Rf can be too large to fabricate with a linear resistor (e.g. poly or diffusion resistors); Very often it is fabricated by a MOS resistor where its small conductance is controlled by its gate voltage.